1. Field of the Invention
This invention relates to a computer memory access technique, and more particularly, to a memory access control method and system for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner through the means of switching the memory access operation between a waiting mode and a non-waiting mode based on L1write-back read requests from the CPU.
2. Description of Related Art
In this information age, computers have become an indispensable data processing tool in all walks of life. In the use of computers, performance is a primary concern. Many factors can affect the performance of a computer system, including the speed of the CPU, the type of the primary memory being used, efficiency of memory access control, and so forth. Presently, dynamic random-access memory (DRAM) is widely used as the primary memory of most computer systems. Conventional memory access methods that can help boost the computer performance include, for example, the Fast Page Mode (FPM) method and the Extended Data Out (EDO) method. Moreover, a new type of DRAM, called synchronized DRAM (SDRAM), allows fast access speed to the data stored therein.
One conventional solution to enhance memory access performance by CPU is to integrate a fast-speed memory, customarily referred as cache memory, in the CPU. When the CPU makes a request to access data, the CPU may want to write the data in the cache memory back to the memory unit. In this situation, according to the CPU operational method, the CPU issues an L1write-back signal at several clock cycles later after the read request is made by the CPU. Conventional memory access control systems typically operate in such a manner that, for each read request from the CPU, the control interface usually waits to ensure whether the L1write-back signal is issued or not, then performs the actual access operations, such as read or write-back by sending out all related instructions to the memory unit. The CPU therefore reads data from the memory unit or writes data back to the memory unit.
It can be learned from the foregoing description that one drawback to the prior art is that there always exists a wait state for the memory access control system to know whether the L1write-back signal of the current read request is included or not and then actually perform the access operation on the memory unit. Since each wait state is several clock cycles long, it causes the memory access operation to be quite inefficient. The overall system performance of the computer system is therefore poor and there is still room for improvement. In a typical computer system, statistics shows that the overall memory access operation performed by a CPU includes about 60% of read operation, 15% of cache write-back operation, and 25% of write operation. Therefore, the overall system performance of the computer system can be enhanced by solely increasing the speed of the read operation. The prior art, however, is low in read operation since it would frequently stay in wait states for L1write-back signals.
It is therefore an objective of the present invention to provide an improved memory access control method and system for use on a computer system, which can help increase the speed of the read operation by the CPU through the means of transferring each read request promptly to the memory unit without waiting until the L1write-back signal of the read request is issued, so that the overall system performance of the computer system can be enhanced.
It is another objective of the present invention to provide an improved memory access control method and system for use on a computer system, which is capable of switching the memory access operation between a waiting mode and a non-waiting mode based on the current L1write-back condition of the read requests from the CPU. In the waiting mode, each read request is transferred to the memory unit until the L1write-back signal thereof is issued; and in non-waiting mode, the read request is promptly transferred to the memory unit without waiting until its L1write-back signal is issued.
In accordance with the foregoing and other objectives of the present invention, an improved memory access control method and system is provided for use on a computer system to control the memory access operation by the CPU to the memory unit in a more efficient manner.
The memory access control method and system is provided for use on a computer system having a CPU and a memory unit for controlling the memory access operation by the CPU to the memory unit. As the CPU issues a read request a following L1 write-back signal, the system is automatically switched to a wait mode, which needs to wait to see if an L1 write-back signal follows or not. As the system is operated in the wait mode, if a certain series of read requests without a following L1 write-back signal, the system is automatically switched to a non-wait mode. In the non-wait mode, the system can perform the CPU request after the read request is issued without a need to wait to see if an L1 write-back signal follows or not.
The memory access control system of the invention is composed of a CPU interface, a memory control unit, and a mode-switching unit.
The CPU interface is coupled to the CPU, which is capable of being selectively switched to operate between a waiting mode and a non-waiting mode; in the waiting mode, the CPU interface responding to each read request from the CPU in such a manner as to wait until the L1write-back signal of the current read request is received and then issue a corresponding internal read-request signal if the L1write-back signal indicates a cache miss, or a corresponding internal cache write-back request signal if the L1write-back signal indicates a cache hit; and in the non-waiting mode, the CPU interface responding to each read request from the CPU in such a manner that the CPU interface will promptly issue the corresponding internal read-request signal without waiting until the CPU issues the L1write-back signal of the current read request, and in the event that the subsequently issued the L1write-back signal of the current read request indicates a cache hit, promptly issue a read-stop signal for the current read request.
The memory control unit is coupled between the CPU interface and the memory unit, which is capable of performing a read operation on the memory unit in response to each internal read-request signal from the CPU interface, and further in response to the read-stop signal, is capable of abandoning the currently retrieved data from the memory unit demanded by the current read request and then performing a cache write-back operation to write back the subsequent output cache data from the CPU back into the memory unit.
Furthermore, the mode-switching unit is coupled between the CPU interface and the CPU, which is initially set to switch the CPU interface to operate in the waiting mode, and is further capable of detecting whether each read request from the CPU is a cache hit or a cache miss and counting the number of consecutive cache-miss read requests to thereby switch the CPU interface to the non-waiting mode when the count reaches a preset threshold.
The memory access control method comprises the procedural steps of: (1) performing a mode-switching process to switch the memory access operation between a waiting mode and a non-waiting mode; the memory access operation being switched to the waiting mode during the time when the currently issued read requests are each a cache hit, and to the waiting mode when the currently issued read request are each a cache miss; (2) in the waiting mode, responding to each read request from the CPU until the CPU issues the L1write-back signal of the current read request; and (3) in the non-waiting mode, promptly responding to each read request from the CPU without waiting until the CPU issues the L1write-back signal of the current read request.
The mode-switching process includes the substeps of: (1-1) initially setting the memory access operation to the waiting mode; and (1-2) if the number of consecutive cache-miss read requests from the CPU reaches a preset threshold, switching the memory access operation to the non-waiting mode, and subsequently, if any cache-hit read request is issued from the CPU, promptly switching the memory access operation back to the waiting mode.
In the waiting mode, the responding to each read request from the CPU includes the substeps of: (2-1) waiting until the L1write-back signal of the current read request is issued; (2-2) checking whether the L1write-back signal of the current read request indicates a cache hit or a cache miss; (2-3) performing a read operation for the current read request if the L1write-back signal of the current read request indicates a cache miss, and (2-4) performing a cache write-back operation if the L1write-back signal of the current read request indicates a cache hit.
Moreover, in the non-waiting mode, the responding to each read request from the CPU includes the substeps of: (3-1) promptly performing a read operation for the current read request without waiting until the CPU issues the L1write-back signal of the current read request; and (3-2) in the event that the subsequently issued L1write-back signal of the current read request indicates a cache hit, promptly issuing a read-stop signal for the current read request to abandon the currently retrieved data from the memory unit, and then performing a cache write-back operation to write back the subsequent output cache data from the CPU into the memory unit.
The foregoing memory access control method and system of the invention is characterized in the capability of switching the memory access operation between a waiting mode and a non-waiting mode. From practical implementation and testing, it can be learned that the overall memory access performance can be increased by switching between the waiting mode and the non-waiting mode based on the current L1write-back condition of the read requests from the CPU. This further helps increase the overall system performance of the computer system.